Nvidia's problems (and board parters too): Taking off the guard rails.
Nvidia, as both the only GPU manufacturer currently using this connector and co-sponsor of the standard with Dell, need to take some heat for this, but their board partners are not without some blame either.
Starting with the 3090 FE and 3090ti FE, we can see that clear care was taken to balance the load across the pins of the connector, with 3 pairs selected and current balanced between them. This is classic Nvidia board design for as long as I remember. They used to do very good work on their power delivery in this sense, with my assumption being to set an example for partner boards. They are essentially treating the 12-pin as 3 8-pins in this design, balancing current between them to keep them all within 150W or so.
On both the 3090 and 3090ti FE, each pair of 12V pins has its own shunt resistor to monitor current, and some power switching hardware is present to move what I believe are individual VRM phases between the pairs. I need to probe around on the FE PCB some more that what I can gather from pictures to be sure.
Now we get to the 4090 and 5090 FE boards. Both of them combine all 6 12V pins into a single block, meaning no current balancing can be done between pins or pairs of pins. It is literally impossible for the 4090 and 5090, and I assume lower cards in the lineup using this connector, to balance their load as they lack any means to track beyond full connector current.
