Write to Read Delay(tWTR)
Settings: Auto, 1, 2
From Adrian Wong’s site:
http://www.rojakpot.com/
”This BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device. The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance. The 2 Cycles option reduces read performance but it will improve stability, especially at higher clock speeds. It may also allow the memory chips to run at a higher speed. In other words, increasing this delay may allow you to overclock the memory module higher than is normally possible. It is recommended that you select the 1 Cycle option for better memory read performance if you are using DDR266 or DDR333 memory modules. You can also try using the 1 Cycle option with DDR400 memory modules. But if you face stability issues, revert to the default setting of 2 Cycles.”
From the DFI BIOS: “This Bios setting specifies the write to read delay. Samsung calls this TCDLR (last data in to read command). It is measured from the rising edge and following the last non-mask data strobe to the rising edge of the next read command. JDEC usually specifies this as one clock.”
Slight Influence on Bandwidth/Stability.
Suggested Settings for DFI: 1 yields better performance, and 2 yields better stability/over clock. (Lower = Faster)
