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Just testet now But i dont like to share, 4200C16-16 is embarrassing. 4200 15-15 flat @ 48.5ns daily ~ is what i'm known for :d Was debugging some new AGESA CO shenanigans, hence dropped down to rule out issues As A0 b-dies became unstable on last two AGESAs on my 1.68v on them. // AGESA 1.2.0.8...

It basically took ~280-300 continuous days , to reach 2100 FCLK no throttle stability // i think it was ~3 months to reach 2000 1:1 and about 2-3 more for 2067 FCLK But research on Vermeer took ~2 years , to build ontop of foundation from 1usmus (yuri) , who took over Matisse (it relates ~ VDDG...

We both could have phrased it better. IMC itself yes, Physical interface is powered by LDO VDDP That is the lower layer When pushing its clock speed for higher UCLK Sync or not being irrelevant :) It will require a bit more VDDP. Then its SI & required voltage, depends on the procODT supplied &...

CS 1 = -10 CO CS 2 = -20 CO CS 3 = -30 CO Zu viel negative CO erzwingt eine VID Korrektur in den neuen AGESAs (mehr wird angefordert, sollte es zu wenig sein) GDM kostet Latenz Vorschlag: ComboStrike 2 , mit: Min SOC für 980mV VDDG, [GET, unter Last >1.022v] ~ 1.05v Bios input, da LLC...

Nein. Auch "bitte" wird nicht helfen, bei: "was das schon wieder sein soll" Die Information liegt irgendwo auf OCN. Irgendwo zwischen dem AMD 24/7 und den Intel 24/7 Thread. Abseits dem, befindest du dich im falschen Thread AM4 erlaubt keine tREFI Erhöhung und das Zitierte gehört zu DDR5.