[Sammelthread] AMD K8/K9 - Sockel 939 | 940 | 754

[Tzk]

The deal is to know the "real" memory dividers, which are in fact "rational numbers", a fraction of two natural numbers, where the second number, the divisor, is always 3.

For your table this is true, yes. However, if you try to find the smaller fractions which fit the scheme, this is the result. Indeed 143 doesn't seem to fit, as needs a quite high prime number (43) to divide correctly. Even if your bios refuses to apply dividers above 200 (so 216/233/250) you should still be able to set these in windows and they should be applied if you're running a E6 cpu.

Are you sure the 216 divider is correct? I always assumed they just used the inverse of the 183 divider, so 11/12 and 12/11. That'd result in 218,181818.... and not 216,666Mhz. Same for 233: 5/6 is 166, 6/5 is 240. I got a E6 at hand, but never bothered with the >1:1 dividers and just upped the HT.

​

HT clock	dividend	divisor	resulting mem divider
200​	1​	2​	100​
200​	5​	8​	125​
200​	2​	3​	133,33​
200​	43​	60​	143,33​
200​	3​	4​	150​
200​	5​	6​	166,67​
200​	11​	12​	183,33​
200​	1​	1​	200,00​
200​	13​	12​	216,67​
200​	7​	6​	233,33​
200​	5​	4​	250​

EDIT:
Another (wrong) theory i found is that AMD simply adjusts the memory divisor up or down by 1, when selecting smaller or bigger memory divider. This may work for some examples, but as you can see in the tables above it'll fail when we reach very small cpu multipliers and when the combination of mem divider and cpu multiplier will skip some divisors. So this theory is busted.

Divider "250" = CPU multiplier - 3
Divider "233" = CPU multiplier - 2
Divider "216" = CPU multiplier - 1
Divider "200" = CPU multiplier
Divider "183" = CPU multiplier + 1
Divider "166" = CPU multiplier + 2
Divider "150" = CPU multiplier + 3
Divider "140" = CPU multiplier + 4
Divider "133" = CPU multiplier + 5
Divider "125" = CPU multiplier + 6
Divider "100" = CPU multiplier + 7

 

[seafs]

There is no direct connection between reference clock and memory clock. It's totally different from Socket A.
Memory Clock is derived from the Memory controller clock. The mem controller in the K8 architecture always runs at full CPU clock speed, what made the mem controller and access latency so good.
IIRC it is not labelled "memory divider" in the BIOS, but "Memclock mode - Limit" instead. At least that's how it's called in my SuperMicro H8DCE.
[Edit] It's called MemClock Value in the A8N32-SLI manual.

Maybe I should clarify the table.


First you need to calculate the CPU clock speed (which is the memory controller clock speed)
Ref clock x CPU multi = CPU clock
200MHz x 11 = 2200MHz
This is an Athlon64 3700+ or a X2 4400+

Then you calculate the theoretical mem divider by dividing the CPU clock speed by the (true) "memclock value". Lets take 183MHz as example
CPU clock / true memclock value = theoretical mem divider
2200 MHz / (550/3) = 12
Because this is a natural number without comma, it's valid and doesn't need to be rounded up.

Then calculate the true memory clock by dividing CPU clock by the true memory diider
CPU clock / true memory divider = true memory clock
2200MHz / 12 = 183,3333MHz.
Fits perfectly and seems good for your theory of 183MHz --> CPU multi + 1


Now let's take a 4000+ or x2 4800+.
200MHz x 12 = 2400MHz

2400 MHz / (550/3) = 13,09090909090909
This time it is bigger than 13, so round up to the next natural number

Round up 13,09090909 = 14.
Because 2400 MHz / 13 = 184,6153846153846 MHz
This is bigger than 183,333 MHz and would be an overclock (out of spec) for the memory.

2400MHz / 14 = 171,4285714285714MHz
This is your true memory clock, which is way below 183,333 MHz, but totally within spec.
And it is not CPU Multi +1, but CPU multi + 2.

The "problem" is the hidden rounding up of the memory divider to prevent an overclock at stock CPU speed and stock reference clock. This causes a lot of confusion, but there is no magic behind it.


Concerning the mem limiters above 200.... I have no clue what happens in windows, I just tried it one time with my H8DCE, but since I don't have DDR500 registered modules, this could be the reason it didn't work. The BIOS won't overwrite SPD profiles, I presume. Maybe some of you want to try memory overclocking at stock speeds ;-)

 

[Tzk]

It's totally different from Socket A.
Memory Clock is derived from the Memory controller clock. The mem controller in the K8 architecture always runs at full CPU clock speed,

Yes, I’m aware that mem clock depends on the IMC clock which in turn is the same as cpu clock. I’m also aware that AMD will always round up the mem divider resulting in a lower mem clock. So supermicro is right to assume it’s a „do not exceed this memclock“ setting and not an exact memclock value.

This is somewhat stupid from the user perspective but makes sense from an engineering standpoint.

I should’ve clarified my thought on the last table I posted. I assumed that it works like this:
Round up („My divider“ x cpu multi) = mem divider
HT x cpu multi / mem divider = real mem clock

So for multi 9.5 and divider 143 (43/60) it would work like this:
9.5 / 43 x 60 = 13.25 -> 14 is chosen
At HT 200 this is 1900mhz cpu and results in 135Mhz mem clock. That is <143 and should thus fit.

 

[seafs]

Dug a bit into this topic and the table of Oskar Wu and .. there seems to be some oddity.

Optimal HTT Readme

The 183 memClock Value seems to cause some headaches.
Oskar Wu's table states for 2200MHz a mem divider of 13, but I can confirm, that my x2 4400+ with memClock Value 183 had a divider of 12. That's how I achieved 3003MHZ and DDR500. (ref Clock 273MHz)
So, what happened? Apparently Oskar Wu's table is for older CPU revisions, while I used an E6 CPU with the last stepping.

When playing with excel, I tried to find the memClock Value, that would change from mem divider 13 to 12.
When using a value of 183,33333333333 ( eleven times 3 after the comma), you'll get divider 13.
Use 183,333333333333 (twelve times 3 after the comma), then you'll get divider 12.

So it seems that these numbers were hard coded into the CPU/BIOS (or some calculation errors due to lack of precision).
Anyways, my table is only applicable to E6 (and maybe E4) CPUs. For older CPUs you must not use the exact fractions (e.g. 550/3), but some manually written fraction with no more than 11 numbers after the decimal separator.

I noticed some more differences. There are five settings, which have a higher mem divider in Oskar Wu's table compared to my calculation.

CPU clock	memClock Value	Oskar Wu	Rev. E6
1100	183	7	6
2200	183	13	12
3300	183	19	18
4400	183	25	24
4300	143	31	30