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@Tzk please, correct the marking for Hynix ETR-E3C. For x16 chips it should be H5DU5162ETR-E3C. Thank you in advance.

I think it is because Trp was moved to 60h and Trp and Trcd became 2-byte, not 1-byte like before (KT266-333). I've had this issue with KM400 and KM400A - wrong Trp and Tras was shown. Also I always recommend tweaking 6A=FF, gives a slight boost. But I think you should compare registers and SIPs...

Another thing to check is that you are using the same version of Everest. Some versions give weird numbers and cannot be compared to others. I see nothing obvious in the registers. @MadYoshi you have checked you board with 1CPU and 1 memory stick, am I right? And nothing changed?

This is standard for most VIA chipsets: 50, 51 = FF Memory timings (64-67 but only those that are really populated by RAM modules) = 12 6A=FF This should already fix 95% of performance problems. With bad RAM these settings might not work, it's the perfect case to reach.

Thank you. Yes, the CAB1E/CAB2E are an interesting case for overclocking. But since AMD decided to make then seem as normal Venice CPUs, it's almost impossible to detect them by software. I think we can identify them by K8 manufacturing ID (CPU-Z txt report shows this value) but I didn't have...

@Tzk , I remember you tried different memory chips on NF2. Could you remind, how did they behave? Anything worth interest besides Winbond?

Biostar 865g micro 775.

@Tzk @digitalbath @WMDK since it's about AMD, I'll post here. This is one of the good sources about microcode update disassembling and modification. https://files.samantaz.fr/useful_knowledge/studies/usenix/sec17-koppe.pdf It explains CPU microcode ROM, microcode update structure and what...

I've written an article about all those blanks in the Athlon 64 we had so far. Enjoy it if you like the AMD K8 architecture. https://docs.google.com/document/d/1el2MxtWsXVTsgcw0ql7OWZZO0akG1Dm0qUaHWqo4x2U/

Yes, XP has microcode update too. So you want to disable it so it doesn't interfere with the tests. You could try this method (7.2). I've used registry to disable it. Let me know if the device manager method won't work, I'll look for the registry. Thank you for the input about solder/paste...

In fact, it is like assembler, bytecode. At least for AMD there were studies that reverse-engineered microcode updates. I'll give a link if I find it in my notes. Very unlikely. I don't think microcodes are related to FSB. Sometimes yes, some undocumented MSR control various features (think...

I'd suggest to try relax subtimings first of all tRC and tRFC, should give a nice improvement on 512Mbit chips. Very impressive results though. Would be interesting to know their voltage scaling too.

Another small thing about PAT: PAT is not a single technology. In fact it's two settings that work similar: 1) Fast CS# (it's present in all P4 chipsets starting from 845). Gigabyte boards have it as a separate setting with Advanced (ctrl+F1) menu. 2) Faster ADS# strobe (this one is new). I've...

It's a very gray area and always was. Some 3DMark and many PCMark alterations were obvious cheats like repacking texture archives, changing benchmark DLLs and so on. But some fall within the "general tweak" when a certain technique doesn't speed up only the benchmark but the system as a whole...

Kingston 1GB with Infineon BC-6 chips.