============================
| KT880 PCI register by db |
============================

Bus 00, Device 00, Function03
-----------------------------

offset51:50
[15:13]= Bank5/4 MA Map Type (see table below)
[12]   = 0=2T Command; 1=1T Command
[11:9] = Bank7/6 MA Map Type (see table below)
[8]    = 0=2T Command; 1=1T Command
[7:5]  = Bank1/0 MA Map Type (see table below)
[4]    = 0=2T Command; 1=1T Command
[3:1]  = Bank3/2 MA Map Type (see table below)
[0]   = 0=2T Command; 1=1T Command

MA Map Type Encoding
000 = 16MB      8-bit, 9-bit, 10-bit Column Address
001 = ?MB  ?-bit Column Address
010 = ?MB  ?-bit Column Address
011 = ?MB  ?-bit Column Address
100 = ?MB  ?-bit Column Address
101 = ?MB  ?-bit Column Address
110 = 128MB ?-bit Column Address
111 = 256/512MB/1GB ?-bit Column Address


offset 56
[7:6]  = tRAS; 00=6T; 01=7T; 10=8T; 11=9T
[5:4]  = CAS Latency; 00=1.5T; 01=2.0T; 10=2.5T; 11=3.0T
[3:2]  = tRCD; 00=2T; 01=3T; 10=4T; 11=5T
[1:0]  = tRP; 00=2T; 01=3T; 10=4T; 11=5T 

offset 68
[2]    = DRAM Operating Frequency;
	0=DRAM same or faster than CPU
	1=DRAM slower than CPU by 33 or 66MHz
[1]    = DRAM Operating Frequency; 
	0=DRAM/CPU freq difference 0 or 33MHz; 
	1=DRAM/CPU freq difference 66MHz

[0]    = DRAM Operating Frequency Faster Than CPU
	0=DRAM same as or slower than CPU
	1=DRAM faster than CPU by 33 or 66MHz


offset 69
[7:6]  = Bank Interleave; 00=No Interleave; 01=2-way; 10=4-way; 11=reserved

offset 6A
[7-0]  = Refresh Counter (in unit of 16 DRAM CLKs); When set to 00, DRAM refresh is disabled

