Physical & Logical Attributes
| Fundamental Memory Class: | DDR4 SDRAM |
| Module Speed Grade: | DDR4-2400R |
| Base Module Type: | UDIMM (133,35 mm) |
| Module Capacity: | 8 GB |
| Reference Raw Card: | A1 (10 layers) |
| JEDEC Raw Card Designer: | SK hynix |
| Module Nominal Height: | 31 < H <= 32 mm |
| Module Thickness Maximum, Front: | 1 < T <= 2 mm |
| Module Thickness Maximum, Back: | 1 < T <= 2 mm |
| Number of DIMM Ranks: | 1 |
| Address Mapping from Edge Connector to DRAM: | Standard |
| DRAM Device Package: | Standard Monolithic |
| DRAM Device Package Type: | 78-ball FBGA |
| DRAM Device Die Count: | Single die |
| Signal Loading: | Not specified |
| Number of Column Addresses: | 10 bits |
| Number of Row Addresses: | 16 bits |
| Number of Bank Addresses: | 2 bits (4 banks) |
| Bank Group Addressing: | 2 bits (4 groups) |
| DRAM Device Width: | 8 bits |
| Programmed DRAM Density: | 8 Gb |
| Calculated DRAM Density: | 8 Gb |
| Number of DRAM components: | 8 |
| DRAM Page Size: | 1 KB |
| Primary Memory Bus Width: | 64 bits |
| Memory Bus Width Extension: | 0 bits |
| DRAM Post Package Repair: | Not supported |
| Soft Post Package Repair: | Not supported |
DRAM Timing Parameters
| Fine Timebase: | 0,001 ns |
| Medium Timebase: | 0,125 ns |
| CAS Latencies Supported: | 9T, 10T, 11T, 12T,
13T, 14T, 15T, 16T,
18T, 20T |
| Minimum Clock Cycle Time (tCK min): | 0,833 ns (1200,48 MHz) |
| Maximum Clock Cycle Time (tCK max): | 1,600 ns (625,00 MHz) |
| CAS# Latency Time (tAA min): | 13,321 ns |
| RAS# to CAS# Delay Time (tRCD min): | 13,321 ns |
| Row Precharge Delay Time (tRP min): | 13,321 ns |
| Active to Precharge Delay Time (tRAS min): | 32,000 ns |
| Act to Act/Refresh Delay Time (tRC min): | 45,321 ns |
| Normal Refresh Recovery Delay Time (tRFC1 min): | 350,000 ns |
| 2x mode Refresh Recovery Delay Time (tRFC2 min): | 260,000 ns |
| 4x mode Refresh Recovery Delay Time (tRFC4 min): | 160,000 ns |
| Short Row Active to Row Active Delay (tRRD_S min): | 3,300 ns |
| Long Row Active to Row Active Delay (tRRD_L min): | 4,900 ns |
| Write Recovery Time (tWR min): | 15,000 ns |
| Short Write to Read Command Delay (tWTR_S min): | 2,500 ns |
| Long Write to Read Command Delay (tWTR_L min): | 7,500 ns |
| Long CAS to CAS Delay Time (tCCD_L min): | 4,981 ns |
| Four Active Windows Delay (tFAW min): | 21,000 ns |
| Maximum Active Window (tMAW): | 8192*tREFI |
| Maximum Activate Count (MAC): | Unlimited MAC |
| DRAM VDD 1,20 V operable/endurant: | Yes/Yes |
Intel Extreme Memory Profiles
| Profiles Revision: 2.0 |
| Profile 1 (Certified) Enables: Yes |
| Profile 2 (Extreme) Enables: No |
| Profile 1 Channel Config: 1 DIMM/channel |
| XMP Parameter | Profile 1 | Profile 2 |
|---|
| Speed Grade: | DDR4-3200 | N/A |
| DRAM Clock Frequency: | 1600 MHz | N/A |
| Module VDD Voltage Level: | 1,35 V | N/A |
| Minimum DRAM Cycle Time (tCK): | 0,625 ns | N/A |
| CAS Latencies Supported: | 20T,19T,18T,17T,
16T,15T,14T,13T,
12T,11T,10T,9T,
8T,7T | N/A |
| CAS Latency Time (tAA): | 10,000 ns | N/A |
| RAS# to CAS# Delay Time (tRCD): | 11,250 ns | N/A |
| Row Precharge Delay Time (tRP): | 11,250 ns | N/A |
| Active to Precharge Delay Time (tRAS): | 22,500 ns | N/A |
| Active to Active/Refresh Delay Time (tRC): | 45,000 ns | N/A |
| Four Activate Window Delay Time (tFAW): | 21,000 ns | N/A |
| Short Activate to Activate Delay Time (tRRD_S): | 3,000 ns | N/A |
| Long Activate to Activate Delay Time (tRRD_L): | 4,900 ns | N/A |
| Normal Refresh Recovery Delay Time (tRFC1): | 350,000 ns | N/A |
| 2x mode Refresh Recovery Delay Time (tRFC2): | 260,000 ns | N/A |
| 4x mode Refresh Recovery Delay Time (tRFC4): | 160,000 ns | N/A |
| Show delays in clock cycles |